This page is a copy of a great x64 SIMD guide from https://www.officedaytime.com/simd512e/, but adapted for those of us who use C#.

I amended it to include the names of intrinsics from the System.Runtime.Intrinsics.X86 namespace as of .NET Core 3.1 (future versions pending).
These names are hard to find in MSDN documentation, and they differ from both Intel’s instruction names and C++ intrinsics. Hence, here they are.

C# names, when awailable, are written below C++ intrinsics.

♯ — links to MSDN documentation are marked with a sharp sign.

Some methods not included here are available for AVX and AVX2. If you can not find what you want, please try and change class name from SseX to Avx or Avx2.
Same deal with Vector256/Vector128.
AVX512 is completely missing from .NET Core at this point. To highlight only AVX2 instructions, use this link.

x86/x64 SIMD Instruction List (SSE to AVX512)

MMX register (64-bit) instructions are omitted.

S1=SSE  S2=SSE2 S3=SSE3 SS3=SSSE3 S4.1=SSE4.1 S4.2=SSE4.2 V1=AVX V2=AVX2 V5=AVX512

Instructions marked * become scalar instructions (only the lowest element is calculated) when PS/PD/DQ is changed to SS/SD/SI.

C/C++ intrinsic name is written below each instruction in blue.

AVX/AVX2

• Add prefix 'V' to change SSE instruction name to AVX instruction name.
• FP AVX instructions can do 256-bit operations on YMM registers.
• Integer AVX instructions can use YMM registers from AVX2.
• To use 256-bit intrinsics, change prefix _mm to _mm256, and suffix si128 to si256.
• Using YMM registers requires the support from OS (For Windows, 7 update 1 or later is required).
• YMM register is basically separated into 2 lanes (upper 128-bit and lower 128-bit) and operates within each lane. Horizontal operations (unpacks, shuffles, horizontal calculations, byte shifts, conversions) can be anomalous. Check the manuals out carefully.

AVX512

• Instructions noted only "(V5" can be used if CPUID AVX512F flag is on.
• Instructions noted "(V5" and "+xx" can be used only if CPUID AVX512F flag is set and AVX512xx flag is also set.
• Using AVX512 instructions requires the support from OS.
• The features common to most AVX512 instructions ({k1}{z}, {er}/{sae}, bcst) are not mentioned in each instruction. See this -> AVX512 Memo
• Opmask register instructions are here.

This document is intended that you can find the correct instruction name that you are not sure of, and make it possible to search in the manuals. Refer to the manuals before coding.

Intel's manuals -> https://software.intel.com/en-us/articles/intel-sdm

When you find any error or something please post this feedback form or email me to the address at the bottom of this page.

Highlighter    SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX512 to   SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AVX AVX2 AVX512   Color   green yellow pink orange  To make these default, bookmark this page after clicking here.

MOVE     ?MM = XMM / YMM / ZMM

	Integer				Floating-Point			YMM lane (128-bit)
	QWORD	DWORD	WORD	BYTE	Double	Single	Half
?MM whole ?MM/mem	MOVDQA (S2 _mm_load_si128 Sse2.LoadAlignedVector128 ♯ _mm_store_si128 Sse2.StoreAligned ♯ MOVDQU (S2 _mm_loadu_si128 Sse2.LoadVector128 ♯ _mm_storeu_si128 Sse2.Store ♯				MOVAPD (S2 _mm_load_pd Sse2.LoadAlignedVector128 ♯ _mm_loadr_pd _mm_store_pd Sse2.StoreAligned ♯ _mm_storer_pd MOVUPD (S2 _mm_loadu_pd Sse2.LoadVector128 ♯ _mm_storeu_pd Sse2.Store ♯	MOVAPS (S1 _mm_load_ps Sse.LoadAlignedVector128 ♯ _mm_loadr_ps _mm_store_ps Sse.StoreAligned ♯ _mm_storer_ps MOVUPS (S1 _mm_loadu_ps Sse.LoadVector128 ♯ _mm_storeu_ps Sse.Store ♯
	VMOVDQA64 (V5... _mm_mask_load_epi64 _mm_mask_store_epi64 etc VMOVDQU64 (V5... _mm_mask_loadu_epi64 _mm_mask_store_epi64 etc	VMOVDQA32 (V5... _mm_mask_load_epi32 _mm_mask_store_epi32 etc VMOVDQU32 (V5... _mm_mask_loadu_epi32 _mm_mask_storeu_epi32 etc	VMOVDQU16 (V5+BW... _mm_mask_loadu_epi16 _mm_mask_storeu_epi16 etc	VMOVDQU8 (V5+BW... _mm_mask_loadu_epi8 _mm_mask_storeu_epi8 etc
XMM upper half mem					MOVHPD (S2 _mm_loadh_pd Sse2.LoadHigh ♯ _mm_storeh_pd Sse2.StoreHigh ♯	MOVHPS (S1 _mm_loadh_pi Sse.LoadHigh ♯ _mm_storeh_pi Sse.StoreHigh ♯
XMM upper half XMM lower half						MOVHLPS (S1 _mm_movehl_ps Sse.MoveHighToLow ♯ MOVLHPS (S1 _mm_movelh_ps Sse.MoveLowToHigh ♯
XMM lower half mem	MOVQ (S2 _mm_loadl_epi64 Sse2.LoadScalarVector128 ♯ _mm_storel_epi64 Sse2.StoreScalar ♯				MOVLPD (S2 _mm_loadl_pd Sse2.LoadLow ♯ _mm_storel_pd Sse2.StoreLow ♯	MOVLPS (S1 _mm_loadl_pi Sse.LoadLow ♯ _mm_storel_pi Sse.StoreLow ♯
XMM lowest 1 elem r/m	MOVQ (S2 _mm_cvtsi64_si128 Sse2.X64.ConvertScalarToVector128Int64 ♯ Sse2.X64.ConvertScalarToVector128UInt64 ♯ _mm_cvtsi128_si64 Sse2.X64.ConvertToInt64 ♯ Sse2.X64.ConvertToUInt64 ♯	MOVD (S2 _mm_cvtsi32_si128 Sse2.ConvertScalarToVector128Int32 ♯ Sse2.ConvertScalarToVector128UInt32 ♯ _mm_cvtsi128_si32 Sse2.ConvertToInt32 ♯ Sse2.ConvertToUInt32 ♯
XMM lowest 1 elem XMM/mem	MOVQ (S2 _mm_move_epi64 Sse2.MoveScalar ♯				MOVSD (S2 _mm_load_sd Sse2.LoadScalarVector128 ♯ _mm_store_sd Sse2.StoreScalar ♯ _mm_move_sd Sse2.MoveScalar ♯	MOVSS (S1 _mm_load_ss Sse.LoadScalarVector128 ♯ _mm_store_ss Sse.StoreScalar ♯ _mm_move_ss Sse.MoveScalar ♯
XMM whole 1 elem	TIP 2 _mm_set1_epi64x VPBROADCASTQ (V2 _mm_broadcastq_epi64 Avx2.BroadcastScalarToVector128 ♯	TIP 2 _mm_set1_epi32 VPBROADCASTD (V2 _mm_broadcastd_epi32 Avx2.BroadcastScalarToVector128 ♯	TIP 2 _mm_set1_epi16 VPBROADCASTW (V2 _mm_broadcastw_epi16 Avx2.BroadcastScalarToVector128 ♯	_mm_set1_epi8 VPBROADCASTB (V2 _mm_broadcastb_epi8 Avx2.BroadcastScalarToVector128 ♯	TIP 2 _mm_set1_pd _mm_load1_pd MOVDDUP (S3 _mm_movedup_pd Sse3.MoveAndDuplicate ♯ _mm_loaddup_pd Sse3.LoadAndDuplicateToVector128 ♯	TIP 2 _mm_set1_ps _mm_load1_ps VBROADCASTSS from mem (V1 from XMM (V2 _mm_broadcast_ss Avx.BroadcastScalarToVector128 ♯
YMM / ZMM whole 1 elem	VPBROADCASTQ (V2 _mm256_broadcastq_epi64 Avx2.BroadcastScalarToVector256 ♯	VPBROADCASTD (V2 _mm256_broadcastd_epi32 Avx2.BroadcastScalarToVector256 ♯	VPBROADCASTW (V2 _mm256_broadcastw_epi16 Avx2.BroadcastScalarToVector256 ♯	VPBROADCASTB (V2 _mm256_broadcastb_epi8 Avx2.BroadcastScalarToVector256 ♯	VBROADCASTSD  from mem (V1  from XMM (V2 _mm256_broadcast_sd Avx.BroadcastScalarToVector256 ♯	VBROADCASTSS  from mem (V1  from XMM (V2 _mm256_broadcast_ss Avx.BroadcastScalarToVector256 ♯		VBROADCASTF128 (V1 _mm256_broadcast_ps Avx.BroadcastVector128ToVector256 ♯ _mm256_broadcast_pd Avx.BroadcastVector128ToVector256 ♯ VBROADCASTI128 (V2 _mm256_broadcastsi128_si256 Avx2.BroadcastVector128ToVector256 ♯
YMM / ZMM whole 2/4/8 elems	VBROADCASTI64X2 (V5+DQ... _mm512_broadcast_i64x2 VBROADCASTI64X4 (V5 _mm512_broadcast_i64x4	VBROADCASTI32X2 (V5+DQ... _mm512_broadcast_i32x2 VBROADCASTI32X4 (V5... _mm512_broadcast_i32x4 VBROADCASTI32X8 (V5+DQ _mm512_broadcast_i32x8			VBROADCASTF64X2 (V5+DQ... _mm512_broadcast_f64x2 VBROADCASTF64X4 (V5 _mm512_broadcast_f64x4	VBROADCASTF32X2 (V5+DQ... _mm512_broadcast_f32x2 VBROADCASTF32X4 (V5... _mm512_broadcast_f32x4 VBROADCASTF32X8 (V5+DQ _mm512_broadcast_f32x8
?MM multiple elems	_mm_set_epi64x Vector256.Create ♯ _mm_setr_epi64x	_mm_set_epi32 Vector256.Create ♯ _mm_setr_epi32	_mm_set_epi16 Vector256.Create ♯ _mm_setr_epi16	_mm_set_epi8 Vector256.Create ♯ _mm_setr_epi8	_mm_set_pd Vector256.Create ♯ _mm_setr_pd	_mm_set_ps Vector256.Create ♯ _mm_setr_ps
?MM whole zero	TIP 1 _mm_setzero_si128 Vector256`1.Zero ♯				TIP 1 _mm_setzero_pd Vector256`1.Zero ♯	TIP 1 _mm_setzero_ps Vector256`1.Zero ♯
extract	PEXTRQ (S4.1 _mm_extract_epi64 Sse41.X64.Extract ♯	PEXTRD (S4.1 _mm_extract_epi32 Sse41.Extract ♯	PEXTRW to r (S2 PEXTRW to r/m (S4.1 _mm_extract_epi16 Sse2.Extract ♯	PEXTRB (S4.1 _mm_extract_epi8 Sse41.Extract ♯	->MOVHPD (S2 _mm_loadh_pd Sse2.LoadHigh ♯ _mm_storeh_pd Sse2.StoreHigh ♯ ->MOVLPD (S2 _mm_loadl_pd Sse2.LoadLow ♯ _mm_storel_pd Sse2.StoreLow ♯	EXTRACTPS (S4.1 _mm_extract_ps Sse41.Extract ♯		VEXTRACTF128 (V1 _mm256_extractf128_ps Avx.ExtractVector128 ♯ _mm256_extractf128_pd Avx.ExtractVector128 ♯ _mm256_extractf128_si256 Avx.ExtractVector128 ♯ VEXTRACTI128 (V2 _mm256_extracti128_si256 Avx2.ExtractVector128 ♯
	VEXTRACTI64X2 (V5+DQ... _mm512_extracti64x2_epi64 VEXTRACTI64X4 (V5 _mm512_extracti64x4_epi64	VEXTRACTI32X4 (V5... _mm512_extracti32x4_epi32 VEXTRACTI32X8 (V5+DQ _mm512_extracti32x8_epi32			VEXTRACTF64X2 (V5+DQ... _mm512_extractf64x2_pd VEXTRACTF64X4 (V5 _mm512_extractf64x4_pd	VEXTRACTF32X4 (V5... _mm512_extractf32x4_ps VEXTRACTF32X8 (V5+DQ _mm512_extractf32x8_ps
insert	PINSRQ (S4.1 _mm_insert_epi64 Sse41.X64.Insert ♯	PINSRD (S4.1 _mm_insert_epi32 Sse41.Insert ♯	PINSRW (S2 _mm_insert_epi16 Sse2.Insert ♯	PINSRB (S4.1 _mm_insert_epi8 Sse41.Insert ♯	->MOVHPD (S2 _mm_loadh_pd Sse2.LoadHigh ♯ _mm_storeh_pd Sse2.StoreHigh ♯ ->MOVLPD (S2 _mm_loadl_pd Sse2.LoadLow ♯ _mm_storel_pd Sse2.StoreLow ♯	INSERTPS (S4.1 _mm_insert_ps Sse41.Insert ♯		VINSERTF128 (V1 _mm256_insertf128_ps Avx.InsertVector128 ♯ _mm256_insertf128_pd Avx.InsertVector128 ♯ _mm256_insertf128_si256 Avx.InsertVector128 ♯ VINSERTI128 (V2 _mm256_inserti128_si256 Avx2.InsertVector128 ♯
	VINSERTI64X2 (V5+DQ... _mm512_inserrti64x2 VINSERTI64X4 (V5... _mm512_inserti64x4	VINSERTI32X4 (V5... _mm512_inserti32x4 VINSERTI32X8 (V5+DQ _mm512_inserti32x8			VINSERTF64X2 (V5+DQ... _mm512_insertf64x2 VINSERTF64X4 (V5 _mm512_insertf64x4	VINSERTF32X4 (V5... _mm512_insertf32x4 VINSERTF32X8 (V5+DQ _mm512_insertf32x8
unpack	PUNPCKHQDQ (S2 _mm_unpackhi_epi64 Sse2.UnpackHigh ♯ PUNPCKLQDQ (S2 _mm_unpacklo_epi64 Sse2.UnpackLow ♯	PUNPCKHDQ (S2 _mm_unpackhi_epi32 Sse2.UnpackHigh ♯ PUNPCKLDQ (S2 _mm_unpacklo_epi32 Sse2.UnpackLow ♯	PUNPCKHWD (S2 _mm_unpackhi_epi16 Sse2.UnpackHigh ♯ PUNPCKLWD (S2 _mm_unpacklo_epi16 Sse2.UnpackLow ♯	PUNPCKHBW (S2 _mm_unpackhi_epi8 Sse2.UnpackHigh ♯ PUNPCKLBW (S2 _mm_unpacklo_epi8 Sse2.UnpackLow ♯	UNPCKHPD (S2 _mm_unpackhi_pd Sse2.UnpackHigh ♯ UNPCKLPD (S2 _mm_unpacklo_pd Sse2.UnpackLow ♯	UNPCKHPS (S1 _mm_unpackhi_ps Sse.UnpackHigh ♯ UNPCKLPS (S1 _mm_unpacklo_ps Sse.UnpackLow ♯
shuffle/permute	VPERMQ (V2 _mm256_permute4x64_epi64 Avx2.Permute4x64 ♯ VPERMI2Q (V5... _mm_permutex2var_epi64	PSHUFD (S2 _mm_shuffle_epi32 Sse2.Shuffle ♯ VPERMD (V2 _mm256_permutevar8x32_epi32 Avx2.PermuteVar8x32 ♯ _mm256_permutexvar_epi32 VPERMI2D (V5... _mm_permutex2var_epi32	PSHUFHW (S2 _mm_shufflehi_epi16 Sse2.ShuffleHigh ♯ PSHUFLW (S2 _mm_shufflelo_epi16 Sse2.ShuffleLow ♯ VPERMW (V5+BW... _mm_permutexvar_epi16 VPERMI2W (V5+BW... _mm_permutex2var_epi16	PSHUFB (SS3 _mm_shuffle_epi8 Ssse3.Shuffle ♯	SHUFPD (S2 _mm_shuffle_pd Sse2.Shuffle ♯ VPERMILPD (V1 _mm_permute_pd Avx.Permute ♯ _mm_permutevar_pd Avx.PermuteVar ♯ VPERMPD (V2 _mm256_permute4x64_pd Avx2.Permute4x64 ♯ VPERMI2PD (V5... _mm_permutex2var_pd	SHUFPS (S1 _mm_shuffle_ps Sse.Shuffle ♯ VPERMILPS (V1 _mm_permute_ps Avx.Permute ♯ _mm_permutevar_ps Avx.PermuteVar ♯ VPERMPS (V2 _mm256_permutevar8x32_ps Avx2.PermuteVar8x32 ♯ VPERMI2PS (V5... _mm_permutex2var_ps		VPERM2F128 (V1 _mm256_permute2f128_ps Avx.Permute2x128 ♯ _mm256_permute2f128_pd Avx.Permute2x128 ♯ _mm256_permute2f128_si256 Avx.Permute2x128 ♯ VPERM2I128 (V2 _mm256_permute2x128_si256 Avx2.Permute2x128 ♯
	VSHUFI64X2 (V5... _mm512_shuffle_i64x2	VSHUFI32X4 (V5... _mm512_shuffle_i32x4			VSHUFF64X2 (V5... _mm512_shuffle_f64x2	VSHUFF32X4 (V5... _mm512_shuffle_f32x4
blend	VPBLENDMQ (V5... _mm_mask_blend_epi32	VPBLENDD (V2 _mm_blend_epi32 Avx2.Blend ♯ VPBLENDMD (V5... _mm_mask_blend_epi32	PBLENDW (S4.1 _mm_blend_epi16 Sse41.Blend ♯ VPBLENDMW (V5+BW... _mm_mask_blend_epi16	PBLENDVB (S4.1 _mm_blendv_epi8 Sse41.BlendVariable ♯ VPBLENDMB (V5+BW... _mm_mask_blend_epi8	BLENDPD (S4.1 _mm_blend_pd Sse41.Blend ♯ BLENDVPD (S4.1 _mm_blendv_pd Sse41.BlendVariable ♯ VBLENDMPD (V5... _mm_mask_blend_pd	BLENDPS (S4.1 _mm_blend_ps Sse41.Blend ♯ BLENDVPS (S4.1 _mm_blendv_ps Sse41.BlendVariable ♯ VBLENDMPS (V5... _mm_mask_blend_ps
move and duplicate					MOVDDUP (S3 _mm_movedup_pd Sse3.MoveAndDuplicate ♯ _mm_loaddup_pd Sse3.LoadAndDuplicateToVector128 ♯	MOVSHDUP (S3 _mm_movehdup_ps Sse3.MoveHighAndDuplicate ♯ MOVSLDUP (S3 _mm_moveldup_ps Sse3.MoveLowAndDuplicate ♯
mask move	VPMASKMOVQ (V2 _mm_maskload_epi64 Avx2.MaskLoad ♯ _mm_maskstore_epi64 Avx2.MaskStore ♯	VPMASKMOVD (V2 _mm_maskload_epi32 Avx2.MaskLoad ♯ _mm_maskstore_epi32 Avx2.MaskStore ♯			VMASKMOVPD (V1 _mm_maskload_pd Avx.MaskLoad ♯ _mm_maskstore_pd Avx.MaskStore ♯	VMASKMOVPS (V1 _mm_maskload_ps Avx.MaskLoad ♯ _mm_maskstore_ps Avx.MaskStore ♯
extract highest bit				PMOVMSKB (S2 _mm_movemask_epi8 Sse2.MoveMask ♯	MOVMSKPD (S2 _mm_movemask_pd Sse2.MoveMask ♯	MOVMSKPS (S1 _mm_movemask_ps Sse.MoveMask ♯
	VPMOVQ2M (V5+DQ... _mm_movepi64_mask	VPMOVD2M (V5+DQ... _mm_movepi32_mask	VPMOVW2M (V5+BW... _mm_movepi16_mask	VPMOVB2M (V5+BW... _mm_movepi8_mask
gather	VPGATHERDQ (V2 _mm_i32gather_epi64 Avx2.GatherVector128 ♯ _mm_mask_i32gather_epi64 Avx2.GatherMaskVector128 ♯ VPGATHERQQ (V2 _mm_i64gather_epi64 Avx2.GatherVector128 ♯ _mm_mask_i64gather_epi64 Avx2.GatherMaskVector128 ♯	VPGATHERDD (V2 _mm_i32gather_epi32 Avx2.GatherVector128 ♯ _mm_mask_i32gather_epi32 Avx2.GatherMaskVector128 ♯ VPGATHERQD (V2 _mm_i64gather_epi32 Avx2.GatherVector128 ♯ _mm_mask_i64gather_epi32 Avx2.GatherMaskVector128 ♯			VGATHERDPD (V2 _mm_i32gather_pd Avx2.GatherVector128 ♯ _mm_mask_i32gather_pd Avx2.GatherMaskVector128 ♯ VGATHERQPD (V2 _mm_i64gather_pd Avx2.GatherVector128 ♯ _mm_mask_i64gather_pd Avx2.GatherMaskVector128 ♯	VGATHERDPS (V2 _mm_i32gather_ps Avx2.GatherVector128 ♯ _mm_mask_i32gather_ps Avx2.GatherMaskVector128 ♯ VGATHERQPS (V2 _mm_i64gather_ps Avx2.GatherVector128 ♯ _mm_mask_i64gather_ps Avx2.GatherMaskVector128 ♯
scatter	VPSCATTERDQ (V5... _mm_i32scatter_epi64 _mm_mask_i32scatter_epi64 VPSCATTERQQ (V5... _mm_i64scatter_epi64 _mm_mask_i64scatter_epi64	VPSCATTERDD (V5... _mm_i32scatter_epi32 _mm_mask_i32scatter_epi32 VPSCATTERQD (V5... _mm_i64scatter_epi32 _mm_mask_i64scatter_epi32			VSCATTERDPD (V5... _mm_i32scatter_pd _mm_mask_i32scatter_pd VSCATTERQPD (V5... _mm_i64scatter_pd _mm_mask_i64scatter_pd	VSCATTERDPS (V5... _mm_i32scatter_ps _mm_mask_i32scatter_ps VSCATTERQPS (V5... _mm_i64scatter_ps _mm_mask_i64scatter_ps
compress	VPCOMPRESSQ (V5... _mm_mask_compress_epi64 _mm_mask_compressstoreu_epi64	VPCOMPRESSD (V5... _mm_mask_compress_epi32 _mm_mask_compressstoreu_epi32			VCOMPRESSPD (V5... _mm_mask_compress_pd _mm_mask_compressstoreu_pd	VCOMPRESSPS (V5... _mm_mask_compress_ps _mm_mask_compressstoreu_ps
expand	VEXPANDQ (V5... _mm_mask_expand_epi64 _mm_mask_expandloadu_epi64	VEXPANDD (V5... _mm_mask_expand_epi32 _mm_mask_expandloadu_epi32			VEXPANDPD (V5... _mm_mask_expand_pd _mm_mask_expandloadu_pd	VEXPANDPS (V5... _mm_mask_expand_ps _mm_mask_expandloadu_ps
align right	VALIGNQ (V5... _mm_alignr_epi64	VALIGND (V5... _mm_alignr_epi32		PALIGNR (SS3 _mm_alignr_epi8 Ssse3.AlignRight ♯
expand Opmask bits	VPMOVM2Q (V5+DQ... _mm_movm_epi64	VPMOVM2D (V5+DQ... _mm_movm_epi32	VPMOVM2W (V5+BW... _mm_movm_epi16	VPMOVM2B (V5+BW... _mm_movm_epi8

Conversions

Arithmetic Operations

Compare

Bitwise Logical Operations

Bit Shift / Rotate

Byte Shift

Compare Strings

Others

TIPS

TIP 1: Zero Clear

XOR instructions do for both Integer and Floating-point.

Example: Zero all of 2 QWORDS / 4 DWORDS / 8 WORDS / 16 BYTES in XMM1

        pxor         xmm1, xmm1

Example: Set 0.0f to 4 floats in XMM1

        xorps        xmm1, xmm1

Example: Set 0.0 to 2 doubles in XMM1

        xorpd        xmm1, xmm1

TIP 2: Copy the lowest 1 element to other elements in XMM register

Shuffle instructions do.

Example: Copy the lowest float element to other 3 elements in XMM1.

        shufps       xmm1, xmm1, 0

Example: Copy the lowest WORD element to other 7 elements in XMM1

        pshuflw       xmm1, xmm1, 0
        pshufd        xmm1, xmm1, 0

Example: Copy the lower QWORD element to the upper element in XMM1

        pshufd        xmm1, xmm1, 44h     ; 01 00 01 00 B = 44h

Is this better?

        punpcklqdq    xmm1, xmm1

TIP 3: Integer Sign Extension / Zero Extension

Unpack instructions do.

Example: Zero extend 8 WORDS in XMM1 to DWORDS in XMM1 (lower 4) and XMM2 (upper 4).

        movdqa     xmm2, xmm1     ; src data WORD[7] [6] [5] [4] [3] [2] [1] [0]
        pxor       xmm3, xmm3     ; upper 16-bit to attach to each WORD = all 0
        punpcklwd  xmm1, xmm3     ; lower 4 DWORDS:  0 [3] 0 [2] 0 [1] 0 [0] 
        punpckhwd  xmm2, xmm3     ; upper 4 DWORDS:  0 [7] 0 [6] 0 [5] 0 [4]

Example: Sign extend 16 BYTES in XMM1 to WORDS in XMM1 (lower 8) and XMM2 (upper 8).

        pxor       xmm3, xmm3
        movdqa     xmm2, xmm1
        pcmpgtb    xmm3, xmm1     ; upper 8-bit to attach to each BYTE = src >= 0 ? 0 : -1
        punpcklbw  xmm1, xmm3     ; lower 8 WORDS
        punpckhbw  xmm2, xmm3     ; upper 8 WORDS

Example (intrinsics): Sign extend 8 WORDS in __m128i variable words8 to DWORDS in dwords4lo (lower 4) and dwords4hi (upper 4)

    const __m128i izero = _mm_setzero_si128();
    __m128i words8hi = _mm_cmpgt_epi16(izero, words8);
    __m128i dwords4lo = _mm_unpacklo_epi16(words8, words8hi);
    __m128i dwords4hi = _mm_unpackhi_epi16(words8, words8hi);

TIP 4: Absolute Values of Integers

If an integer value is positive or zero, it is already the abosoute value. Else, adding 1 after complementing all bits makes the absolute value.

Example: Set absolute values of 8 signed WORDS in XMM1 to XMM1

                                  ; if src is positive or 0; if src is negative
        pxor      xmm2, xmm2      
        pcmpgtw   xmm2, xmm1      ; xmm2 <- 0              ; xmm2 <- 1
        pxor      xmm1, xmm2      ; xor with 0(do nothing) ; xor with -1(complement all bits)
        psubw     xmm1, xmm2      ; subtract 0(do nothing) ; subtract -1(add 1)

Example (intrinsics): Set abosolute values of 4 DWORDS in __m128i variable dwords4 to dwords4

    const __m128i izero = _mm_setzero_si128();
    __m128i tmp = _mm_cmpgt_epi32(izero, dwords4);
    dwords4 = _mm_xor_si128(dwords4, tmp);
    dwords4 = _mm_sub_epi32(dwords4, tmp);

TIPS 5: Absolute Values of Floating-Points

Floating-Points are not complemented so just clearing sign (the highest) bit makes the absolute value.

Example: Set absolute values of 4 floats in XMM1 to XMM1

; data
              align   16
signoffmask   dd      4 dup (7fffffffH)       ; mask for clearing the highest bit
        
; code
        andps   xmm1, xmmword ptr signoffmask        

Example (intrinsics): Set absolute values of 4 floats in __m128 variable floats4 to floats4

        const __m128 signmask = _mm_set1_ps(-0.0f); // 0x80000000

        floats4 = _mm_andnot_ps(signmask, floats4);

TIP 6: Lacking some integer MUL instructions?

Signed/unsigned makes difference only for the calculation of the upper part. Fot the lower part, the same instruction can be used both for signed and unsigned.

unsigned WORD * unsigned WORD -> Upper WORD: PMULHUW, Lower WORD: PMULLW

singed WORD * signed WORD -> Upper WORD: PMULHW, Lower WORD: PMULLW

TIP 8: max / min

Bitwise operation after getting mask by compararison does.

Example: Compare each signed DWORD in XMM1 and XMM2 and set smaller one to XMM1

; A=xmm1  B=xmm2                    ; if A>B        ; if A<=B
        movdqa      xmm0, xmm1
        pcmpgtd     xmm1, xmm2      ; xmm1=-1       ; xmm1=0
        pand        xmm2, xmm1      ; xmm2=B        ; xmm2=0
        pandn       xmm1, xmm0      ; xmm1=0        ; xmm1=A
        por         xmm1, xmm2      ; xmm1=B        ; xmm1=A

Example (intrinsics): Compare each signed byte in __m128i variables a, b and set larger one to maxAB

    __m128i mask = _mm_cmpgt_epi8(a, b);
    __m128i selectedA = _mm_and_si128(mask, a);
    __m128i selectedB = _mm_andnot_si128(mask, b);
    __m128i maxAB = _mm_or_si128(selectedA, selectedB);

TIP 10: Set all bits

PCMPEQx instruction does.

Example: set -1 to all of the 2 QWORDS / 4 DWORDS / 8 WORDS / 16 BYTES in XMM1.

        pcmpeqb         xmm1, xmm1

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